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Clock distribution networks are vital for the synchronization of digital ICs while constituting the significant portion of total power consumption. To this end, design methodologies for clock networks are well-studied in the literature and industrial applications to address the tradeoff between timing performance and power consumption. Low power techniques, such as voltage scaling and clock gating, are introduced to minimize power consumption, however, their application remains limited due to their performance overhead. High performance topologies, such as clock meshes, are promising to deliver high timing performance while suffering from high power consumption.

The proposed research targets to achieve high performance and low power concurrently by studying voltage-scaled clock networks: (1) Power minimization for clock mesh topology through multi-voltage design while preserving the high timing performance and (2) performance optimization for clock tree topology through low swing clocking while preserving low power consumption. For each theme [(1) and (2)], the proposed research performs 3 main tasks: i) the feasibility study, ii) design methodologies for automation and iii) variation-awareness for yield improvement. Furthermore, 2 additional tasks (clock gating integration and FinFET-based design) are performed for low swing clocking theme to address missing approaches in the literature as well as meet the technology transfer demands of the microelectronics industry.