| Start Date: | 5/15/2014 | Start Time: | 2:00 PM |
| End Date: | 5/15/2014 | End Time: | 4:00 PM |
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Event Description
Speaker: Dr. Mircea R. Stan, University of Virginia
Thursday, May 15, 2014 at 2:00 p.m.
ECE Conference Room 302, 3rd Floor Bossone Research Enterprise Center
Abstract
The power delivery walls include: power density (power consumption density increases beyond the heat dissipation capabilities of the technology), power and ground power delivery pins (chip power consumption requires increasing numbers of pins), 3DIC power density (physical stacking in the third dimension exacerbates the two-dimensional explosion), and on-chip power regulation efficiency (relatively poor efficiencies achievable with on-chip regulators limit the effectiveness of many low power schemes). In this talk we demonstrate how voltage stacking is a comprehensive method for addressing the power delivery walls above, with special emphasis on 3DIC.
Bio
Mircea R. Stan received the Ph.D. and M.S. degrees in Electrical and Computer Engineering from the University of Massachusetts at Amherst. Since 1996 he has been with the Department of Electrical and Computer Engineering at the University of Virginia, where he is now a professor. Prof. Stan is teaching and doing research in the areas of high-performance low-power VLSI, temperature aware circuits and architecture, embedded systems, and nanoelectronics. He has received the NSF CAREER award in 1997 and was a coauthor on best paper awards at ISQED 2008, GLSVLSI 2006, ISCA 2003 and SHAMAN 2002.
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Location:
ECE Conference Room 302, 3rd floor Bossone Enterprise Research Center |
Audience:
AlumniCurrent StudentsFacultyStaff |
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