Event Description
Dr. Ravi Iyer, Intel
Thursday, June 5, 2014 at 2:00 p.m.
ECE Conference Room 302, 3rd Floor, Bossone Research Enterprise Center
Abstract:
With the rapid emergence of compute devices (extremely small sensor nodes to highly parallel cloud platforms) and rich domain of applications (sensing, speech, vision, analytics), architects and researchers have a new set of challenges and opportunities. This ranges from how to achieve low power (on one hand) to how to integrate more intelligence (on the other hand). In this talk, I will provide some motivation for these seemingly opposing forces and outline a set of challenges that faces future computer architectures (power, performance, scalability, etc). I will also describe opportunities for future research for ultra-low power SoCs. This includes considerations for heterogeneity, QoS, accelerators, memory hierarchies and energy harvesting. I will provide some examples of on-going research in these areas to demonstrate possible solutions for the future.
Bio:
Ravi Iyer is a Senior Principal Engineer in Intel Labs and also Director of Module Integration Lab. He conducts research on next-generation architectures (e.g. SoC/CMP) for integrated platforms (e.g. IOT/wearables) including accelerators, cache/memory, QoS, emerging workloads, and power/performance analysis. He has published over 150 technical papers in the above areas. Ravi has 15+ patents issued and 30+ patent applications pending. He frequently participates in journals, conferences and workshops. He is currently an associate editor for ACM TACO. He recently served as the General Chair for IISWC 2013, General Co-Chair for ISCA 2011 and Program Co-Chair for CASES 2014 and ANCS 2010.
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