Event Description
IEEE Council on Electronic Design Automation (CEDA) sponsored
Drexel Computer Engineering Invited Speaker
Soft-Error Tolerant Datapath Synthesis Based on Speculative Resource Sharing
Junghoon Oh, Visiting Researcher, Japan Advanced Institute of Science and Technology
Abstract
As semiconductor technologies have advanced, the reliability problem caused by soft-errors is becoming one of the serious issues in VLSI. Moreover, multiple component errors due to single soft-errors also have become a serious problem. In this talk, we propose a method to synthesize multiple component soft-error tolerant application-specific datapaths via high-level synthesis. The novel feature of our method is speculative resource sharing between the retry parts and the secondary parts for time overhead mitigation. A scheduling algorithm using a special priority function to maximize speculative resource sharing is also an important feature of this study. Our approach can reduce the latency (schedule length) in many applications without deterioration of reliability and chip area compared with conventional datapaths without speculative resource sharing. We also found that our method is more effective when a computation algorithm possesses higher parallelism and a smaller number of resources are available.
Speaker Biography
Junghoon Oh was born in Seoul, South Korea. After he earned his bachelor’s degree, he worked in industry as an embedded software engineer in Korea and Japan for 8 years. He received his master’s degree in information science from Japan Advanced Institute of Science and Technology (JAIST) in 2014. He is pursuing a Ph.D degree at JAIST and currently studying in the Drexel VLSI lab in the ECE department as a visiting researcher (supervised by Dr. Taskin). His research interests are CAD systems based on high-level synthesis and fault-tolerant VLSIs/systems.
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