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Abstract

Rather than improving single-threaded performance, with the dawn of the multi-core era, processor micro-architects have exploited Moore’s law transistor scaling by increasing core density on a chip and increasing the number of thread contexts within a core. However, single-thread performance and efficiency is still very relevant in the power-constrained multi-core era.

This dissertation provides a detailed study of register reference count structures and its application to both conventional and non-conventional out-of-order processors. A study of register allocation algorithms shows how register file occupancy can be exploited to dynamically re-size the register file to reduce power consumption, which is especially important in the face of wider multithreaded processors. We show how reference counting can ‘pin’ registers during checkpointed execution, rather than incorporating shadow-bitcells, which increase register file area and leakage costs. Finally we build hardware models of reference count structures and show that the area and overheads are low relative to conventional register management mechanisms and are recouped by the techniques that reference counting enables.

This dissertation leverages these register management structures to introduces a new load latency tolerant micro-architecture. This micro-architecture incorporates a novel predictive approach to scale the instruction window, improving performance during low ILP regions of execution. The key features include a front-end predictive slice-out mechanism and in-order queue structure, mechanisms to reduce the energy cost of dynamic instruction execution by eliminating costly issue-queue broadcasts for sliced instructions, and a mechanism to share register file resources across multiple instructions.